march 1995 revised april 1999 74lcx574 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs ? 1999 fairchild semiconductor corporation ds012406.prf www.fairchildsemi.com 74lcx574 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs general description the lcx574 is a high-speed, low power octal flip-flop with a buffered common clock (cp) and a buffered common output enable (oe ). the information presented to the d inputs is stored in the flip-flops on the low-to-high clock (cp) transition. the lcx574 is functionally identical to the lcx374 except for the pinouts. the lcx574 is designed for low voltage (2.5v or 3.3v) v cc applications with capability of interfacing to a 5v signal environment. the lcx574 is fabricated with an advanced cmos technology to achieve high speed operation while maintaining cmos low power dissipation. features n 5v tolerant inputs and outputs n 2.3vC3.6v v cc specifications provided n 7.5 ns t pd max (v cc = 3.3v), 10 m a i cc max n power down high impedance inputs and outputs n supports live insertion/withdrawal (note 1) n 24 ma output drive (v cc = 3.0v) n implements patented noise/emi reduction circuitry n latch-up performance exceeds 500 ma n esd performance: human body model > 2000v machine model > 200v note 1: to ensure the high-impedance state during power up or down, oe should be tied to v cc through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. logic symbol pin descriptions connection diagram order number package number package description 74lcx574wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide 74lcx574sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lcx574msa msa20 20-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide 74lcx574mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description d 0 Cd 7 data inputs cp clock pulse input oe 3-state output enable input o 0 Co 7 3-state outputs
www.fairchildsemi.com 2 74lcx574 functional description the lcx574 consists of eight edge-triggered flip-flops with individual d-type inputs and 3-state true outputs. the buffered clock and buffered output enable are common to all flip-flops. the eight flip-flops will store the state of their individual d inputs that meet the setup and hold time requirements on the low-to-high clock (cp) transition. with the output enable (oe ) low, the contents of the eight flip-flops are available at the outputs. when oe is high, the outputs go to the high impedance state. opera- tion of the oe input does not affect the state of the flip- flops. truth table h = high voltage level l = low voltage level x = immate rial z = high impedance = low-to-high transition nc = no change logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays. inputs internal outputs function oe cp d q o n h h l nc z hold h h h nc z hold h l l z load h h h z load l l l l data available l h h h data available l h l nc nc no change in data l h h nc nc no change in data
3 www.fairchildsemi.com 74lcx574 absolute maximum ratings (note 2) recommended operating conditions (note 4) note 2: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maxi m um ratings. the recom- mended operating conditions table will define the conditions for actual device operation. note 3: i o absolute maximum rating must be observed. note 4: unused inputs must be held high or low. they may not float. dc electrical characteristics symbol parameter value conditions units v cc supply voltage - 0.5 to + 7.0 v v i dc input voltage - 0.5 to + 7.0 v v o dc output voltage - 0.5 to + 7.0 output in 3-state v - 0.5 to v cc + 0.5 output in high or low state (note 3) i ik dc input diode current - 50 v i < gnd ma i ok dc output diode current - 50 v o < gnd ma + 50 v o > v cc i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature - 65 to + 150 c symbol parameter min max units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 05.5v v o output voltage high or low state 0 v cc v 3-state 0 5.5 i oh /i ol output current v cc = 3.0v - 3.6v 24 ma v cc = 2.7v - 3.0v 12 v cc = 2.3v - 2.7v 8 t a free-air operating temperature - 40 85 c d t/ d v input edge rate, v in = 0.8vC2.0v, v cc = 3.0v 0 10 ns/v symbol parameter conditions v cc t a = - 40 c to + 85 c units (v) min max v ih high level input voltage 2.3 - 2.7 1.7 v 2.7 - 3.6 2.0 v il low level input voltage 2.3 - 2.7 0.7 v 2.7 - 3.6 0.8 v oh high level output voltage i oh = - 100 m a2.3 - 3.6 v cc - 0.2 v i oh = - 8ma 2.3 1.8 i oh = - 12 ma 2.7 2.2 i oh = - 18 ma 3.0 2.4 i oh = - 24 ma 3.0 2.2 v ol low level output voltage i ol = 100 m a2.3 - 3.6 0.2 v i ol = 8 ma 2.3 0.6 i ol = 12 ma 2.7 0.4 i ol = 16 ma 3.0 0.4 i ol = 24 ma 3.0 0.55 i i input leakage current 0 v i 5.5v 2.3 - 3.6 5.0 m a i oz 3-state output leakage 0 v o 5.5v 2.3 - 3.6 5.0 m a v i = v ih or v il i off power-off leakage current v i or v o = 5.5v 0 10 m a
www.fairchildsemi.com 4 74lcx574 dc electrical characteristics (continued) note 5: outputs disabled or 3-state only. ac electrical characteristics note 6: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). dynamic switching characteristics capacitance symbol parameter conditions v cc t a = - 40 c to + 85 c units (v) min max i cc quiescent supply current v i = v cc or gnd 2.3 - 3.6 10 m a 3.6v v i ,v o 5.5v (note 5) 2.3 - 3.6 10 m a d i cc increase in i cc per input v ih = v cc - 0.6v 2.3 - 3.6 500 m a symbol parameter t a = - 40 c to + 85 c, r l = 500 w units v cc = 3.3v 0.3v v cc = 2.7v v cc = 2.5 0.2v c l = 50 pf c l = 50 pf c l = 30 pf min max min max min max f max maximum clock frequency 150 mhz t phl propagation delay 1.5 8.5 1.5 9.5 1.5 10.5 ns t plh cp to o n 1.5 8.5 1.5 9.5 1.5 10.5 t pzl output enable time 1.5 8.5 1.5 9.5 1.5 10.5 ns t pzh 1.5 8.5 1.5 9.5 1.5 10.5 t plz output disable time 1.5 6.5 1.5 7.0 1.5 7.8 ns t phz 1.5 6.5 1.5 7.0 1.5 7.8 t s setup time 2.5 2.5 4.0 ns t h hold time 1.5 1.5 2.0 ns t w pulse width 3.3 3.3 4.0 ns t oshl output to output skew (note 6) 1.0 ns t oslh 1.0 symbol parameter conditions v cc (v) t a = 25 c units typical v olp quiet output dynamic peak v ol c l = 50 pf, v ih = 3.3v, v il = 0v 3.3 0.8 v c l = 30 pf, v ih = 2.5v, v il = 0v 2.5 0.6 v olv quiet output dynamic valley v ol c l = 50 pf, v ih = 3.3v, v il = 0v 3.3 - 0.8 v c l = 30 pf, v ih = 2.5v, v il = 0v 2.5 - 0.6 symbol parameter conditions typical units c in input capacitance v cc = open, v i = 0v or v cc 7pf c out output capacitance v cc = 3.3v, v i = 0v or v cc 8pf c pd power dissipation capacitance v cc = 3.3v, v i = 0v or v cc , f = 10 mhz 25 pf
5 www.fairchildsemi.com 74lcx574 ac loading and waveforms generic for lcx family figure 1. ac test circuit (c l includes probe and jig capacitance) waveform for inverting and non-inverting functions propagation delay. pulse width and t rec waveforms 3-state output low enable and disable times for logic 3-state output high enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall figure 2. waveforms (input characteristics; f =1mhz, t r = t f = 3ns) test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v v cc x 2 at v cc = 2.5 0.2v t pzh ,t phz gnd symbol v cc 3.3v 0.3v 2.7v 2.5v 0.2v v mi 1.5v 1.5v v cc /2 v mo 1.5v 1.5v v cc /2 v x v ol + 0.3v v ol + 0.3v v ol + 0.15v v y v oh - 0.3v v oh - 0.3v v oh - 0.15v
www.fairchildsemi.com 6 74lcx574 schematic diagram generic for lcx family
7 www.fairchildsemi.com 74lcx574 physical dimensions inches (millimeters) unless otherwise noted 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide package number m20b 20-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m20d
www.fairchildsemi.com 8 74lcx574 physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide package number msa20
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. 74lcx574 low voltage octal d-type flip-flop with 5v tolerant inputs and outputs life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc20
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